Fayé Brigs is an Intel Fellow and Director of Scalable Server Architecture for the Digital Enterprise Group. He is responsible for ensuring that Intel’s multi-core and many-core-based server architectures achieve leading performance.
Briggs has had a leadership role in developing multiple generations of innovative multiprocessor server and chipset designs, including all current front-side-bus based Xeon dual and multiprocessor server chipsets and platform architectures. He conceptualized the first Intel point-to-point scalability port for 2P – 16P scalable architecture family of 870 server chipsets for Itanium and Xeon servers and led the development of the devices.
Prior to joining Intel in 1997, Briggs held various positions at Sun Microsystems, including serving as the co-architect of Sun’s original SPARC processor. Briggs was also a co-founder and CTO of Axil Computers, where he led the development of chipsets, boards and systems for more than 30 servers, storage and workstation products. He also served as a tenured associate professor at Rice University and as a faculty member at Purdue University, both in electrical and computer engineering.
Briggs as published numerous technical papers on processor and multiprocessor architectures, memory ordering, cache coherence and system performance. He is the co-author of the McGraw-Hill published textbook, “Computer Architecture and Parallel Processing.” Briggs has been awarded four patents and received an Intel Achievement Award for the successful definition and execution of Intel’s first quad-core products.
Briggs received his bachelor’s degree in engineering in 1971 from Ahmadu Bello University, Nigeria. He received his master’s degree in electrical engineering from Stanford University in 1974, and his doctorate in electrical in electrical and computer engineering from the University of Illinois, Urbana-Champaign in 1977.